paper

Abstract

An integrated circuit for a physical unclonable function (PUF) to generate an identifier for each device is proposed based on the via formation probability. The via hole size is determined to be smaller than that specified by the design rule which guarantees successful via formation. As a result, a via is formed with a certain probability. A proper via hole size and a post-processing method are found to obtain very high randomness in the bit sequences, and it is confirmed that the bit error rate is zero through repeated measurements over one year under the supply voltage variations with noises and in a wide range of temperature. This time invariance of bits can be attributed to the fact that the via formation does not change over time, once they are formed.

This paper compares two types of physical unclonable function (PUF) circuits in terms of reliability, mismatch-based PUF vs. physical-based PUF. Most previous PUF circuits utilize device mismatches for generating random responses. Although they have sufficient random features, there is a reliability issue that some portions of bits are changed over time during operation or under noisy environments. To overcome this issue, we previously proposed the differential amplifier PUF (DA-PUF) which improves the reliability by amplifying the small mismatches of the transistors and rejecting the power supply noise through differential operation. In this paper, we first report the experimental results with the fabricated chips in a 0.35 µm CMOS process. The DA-PUF shows 51.30% uniformity, 50.05% uniqueness, and 0.43% maximum BER. For 0% BER, we proposed the physical-based VIA-PUF which is based on the probability of physical connection between the electrical layers. From the experimental results with the fabricated chips in a 0.18 µm CMOS process, we found the VIA-PUF has 51.12% uniformity and 49.64% uniqueness, and 0% BER throughout 1,000-time repeated measurements. Especially, we have no bit change after the stress test at 25 and 125 °C for 96 hours.

The physical unclonable function (PUF) for generating unique bit strings has been tried using process variations in semiconductor fabrication. It can find various applications in hardware security area such as authentication or secure key storage. The unique secure information should not be changed over time in various environmental conditions such as temperature and supply voltage variations. This requirement is represented by the reliability of a PUF. Most of the previous PUFs are based on the mismatches between two circuit elements such as two transistors with an identical layout. However, in case the mismatches are very minute, the PUF response can be easily affected by changes in the external environments. Moreover, the characteristics can vary with the temperature variation. Some techniques including preselection method and use of error correction code (ECC) have been proposed to overcome this reliability issue, but they need non-volatile memories, and significantly increase the circuit area and the power consumption. On the other hand, the physical-based PUF only makes use of the probability that the conducting layers in a semiconductor chip are physically connected. Once the connection state is determined during a semiconductor process, it is not changed with the temperature or supply voltage variations. The VIA-PUF, one of the physical-based PUFs, can generate the random responses if the via hole size is properly chosen smaller than regulated by the design rule. The VIA-PUF is fabricated in a 0.18μm CMOS process and evaluated with 119 chips, each of which has 2,560 bits. The experiments show that the YIA-PUF shows no bit error throughout 1,000 times repeated measurement for 96 hours at 125 °C.

This article proposes a physical unclonable function (PUF) based on the contact formation probability. The contact here is the interconnect layer between the metal and the silicon in a chip. As the contact is designed smaller than the size given in the design rule, the contact formation becomes stochastic in a certain range of contact hole sizes and can be a random source for the PUF. Consequently, once the contact state is determined to be either open or short, its connectivity does not change over time under noisy environmental conditions, such as temperature, supply voltage, humidity variations, and so on. The reliability of the proposed contact PUF is veriﬁed through seven reliability tests deﬁned by the Joint Electron Device Engineering Council (JEDEC) standards. No bit errors occur in any of the 366 chips tested. The bitcell is designed using a digital standard cell structure and scattered throughout the chip embedded in other logic gates. This makes it difﬁcult to ﬁnd the bitcell position. The proposed contact PUF is fabricated using 0.13-µm CMOS technology. It achieves 49.99% uniqueness and 0.99973 entropy and passes all applicable randomness tests given by the National Institute of Standards and Technology (NIST) SP 800-22.

This study proposes a physical unclonable function (PUF) based on contact failure probability referred to as contact PUF, which has a sufficiently high native stability to achieve mass production without any postprocessing such as error-correction code. The contact is designed to cause stochastic contact failure that is used as the entropy source of the contact PUF. Contact failure can occur in three contact fabrication steps: photolithography, etching, and deposition. We investigated how contact failure occurs in each contact fabrication step in 180 nm, 130 nm, and 28 nm CMOS processes. After the preselection method that discarded unstable bitcells in 180 nm, 130 nm, and 28 nm CMOS processes, no PUF bitcell responses were flipped during 2000 repeated measurements following nine operating conditions, wherein there are three temperatures (−40 °C, 25 °C, and 125 °C) and three supply voltages (nominal, and ±10%). This means that the contact PUFs have bit error rates < 1.03 × 10-8, < 2.3 × 10-8, and < 2.3 × 10-7 in the cases of the 180 nm, 130 nm, and 28 nm CMOS processes, respectively. The discard ratios of the contact PUFs are < 1.03×10-8, 0.0054%, and 0.949% in the respective cases of 180 nm, 130 nm, and 28 nm CMOS processes. The uniqueness of the contact PUFs are respectively equal to 0.4996, 0.49994, and 0.4964 in the 180 nm, 130 nm, and 28 nm CMOS processes.

Preselection methods in which unstable bitcells are discarded are widely used to enhance the stability of the physical unclonable function (PUF). If the discard range of the preselection is too narrow, all unstable bitcells cannot be discarded, whereas, if the discard range is too wide, the PUF circuit area increases because the number of redundant bitcells should increase. Moreover, the discard range of most previous PUFs is not determined by theoretical analysis but rather by repeated measurements, which requires a long test time and cannot determine the accurate discard range to guarantee the PUF stability. This article demonstrates an efﬁcient preselection method to determine the discard range through a theoretical analysis of the PUF entropy source for the PUF based on contact failure probability (contact PUF). After this preselection with the discard ratio of 0.0177%, no PUF responses changed among 2 367 040 bits from 1138 chips, i.e., bit error rate <0.43 ppm, in seven harsh environmental tests regulated by the Joint Electron Device Engineering Council (JEDEC) standard. The proposed preselection method also enables the contact PUF to be implemented in a small area due to the low discard ratio. A small-area design methodology of contact PUF bitcells is also proposed. The PUF bitcell area per bit is 325F2, the smallest area compared to previous PUFs. The contact PUF with the proposed preselection applied is fabricated in 100-nm CMOS technology. It achieves 0.4999 of uniqueness and 0.9942 of Shannon entropy and passes all applicable randomness tests stipulated by the National Institute of Standards and Technology (NIST) SP800-22.

Resource Paper

Resource
　　
Paper